1. Field of the Invention
The present invention generally relates to a PLL frequency synthesizer circuit incorporating a comparison frequency divider having a swallow counter, and, more particularly, to a swallow counter having modulus signal output control.
2. Description of the Related Art
PLL frequency synthesizer circuits, which are operable at a high speeds, are typically used in digital mobile communication devices, such as portable telephones and the like. However, when operating at a high-speed, the internal operations of the logic gates within the PLL frequency synthesizer circuit may experience delays.
A conventional PLL frequency synthesizer circuit usually includes a comparison frequency divider which has a prescaler, a swallow counter and a program counter. A conventional prescaler selectively frequency-divides a frequency signal from a voltage controlled oscillator (VCO) by either a frequency-dividing ratio P or a frequency-dividing ratio (P+X) and supplies complementary frequency-divided signals to the program counter and the swallow counter. As used above, "X" may be a positive or negative integer and "P" may be a positive integer.
The conventional program counter frequency-divides the complementary frequency-divided signals from the prescaler by a predetermined frequency-dividing ratio (e.g., 16) and supplies a comparison signal to a phase comparator. The program counter further counts a predetermined number of (e.g., 16) pulses of the complementary frequency-divided signals CK and XCK, and produces an H-level load signal LOAD during counting or produces an L-level load signal LOAD every time count-up is performed.
The conventional swallow counter counts the pulses of the complementary frequency-divided signals CK and XCK based on a set value supplied from an external unit, and provides the prescaler with an L-level modulus signal MDC which causes the prescaler to change the frequency-dividing ratio. In response to the L-level load signal LOAD supplied from the program counter, the swallow counter further executes a preset operation to restart the counting operation, and supplies an H level modulus signal MDC to the prescaler. In response to the H-level modulus signal MDC, the prescaler sets the changed frequency-dividing ratio back to the one before the alteration. As apparent from the above, the swallow counter controls the switching of the modulus operation (alteration of the frequency-dividing ratio) of the prescaler.
As shown in FIG. 1, the conventional swallow counter has an up-counter section 50, a NAND gate section 58, an RS flip-flop 59, inverters 60 and 63, a NAND gate 61 and a D flip-flop 62. The up-counter section 50 includes seven flip-flops (FFs) 51 to 57. The first to seventh FFs 51-57, respectively, receive seven set value data A1 to A7 supplied from a shift register (not shown). The set value data A1-A7 are binary code data whose set values can be set within a range of 0 to 127 as needed. The first to seventh FFs 51-57 count the pulses of the complementary frequency-divided signals CK and XCK supplied from the prescaler based on the respective set value data A1-A7, and output H-level output signals from complementary output terminals when performing a count-up operation.
The NAND gate section 58, which is connected to the up-counter section 50, includes three NAND gates 58a to 58c and one NOR gate 58d. When the first to seventh FFs 51-57 output H-level output signals from their complementary output terminals, the NAND gate section 58 supplies a L level first output signal SA to the RS flip-flop 59. The RS flip-flop 59, comprised of two NAND gates, has a set input terminal for receiving the first output signal SA and a reset input terminal for receiving the load signal LOAD supplied from the program counter (not shown). The first to seventh FFs 51-57 execute a preset operation of the respective set value data in response to the L-level load signal LOAD.
The RS flip-flop 59 supplies the H-level output signal to the inverter 60 in response to the L-level first output signal SA. In response to the H-level output signal, the inverter 60 supplies a second output signal SB of an L level to the NAND gate 61. Further, the RS flip-flop 59 supplies the L-level output signal to the inverter 60 in response to the L-level load signal LOAD. In response to the L-level output signal, the inverter 60 supplies the second output signal SB of an H level to the NAND gate 61.
The NAND gate 61 has a first input terminal for receiving the second output signal SB, a second input terminal for receiving the load signal LOAD, and an output terminal which is connected to the data input terminal of the D flip-flop 62, and from which a third output signal SC is output. In response to the complementary frequency-divided signals CK and XCK, the D flip-flop 62 sends its output signal which is the third output signal SC (whose level has been inverted), to the inverter 63. The inverter 63 supplies an output signal which is the output signal of the D flip-flop 62 (whose level has also been inverted), to the inverter 63 which is connected to the prescaler (not shown) as the modulus signal MDC. The prescaler changes the frequency-dividing ratio when the modulus signal MDC falls to the L level from the H level. When the RS flip-flop 59 outputs the L-level output signal in response to the L-level load signal LOAD, the modulus signal MDC rises to the H level from the L level. In accordance with this change, the prescaler sets the changed frequency-dividing ratio back to the one before the alteration.
To fix the frequency-dividing ratio of the prescaler, typically, all of the set value data A1-A7 in this swallow counter are set to "0" (i.e., "0" in the decimal notation). FIG. 2 presents a time-line chart illustrating the operation of the swallow counter, as in FIG. 1, when all of the set value data A1-A7 are "0" and the complementary frequency-divided signals CK and XCK have relatively low frequencies.
First, the RS flip-flop 59 supplies the L-level output signal to the inverter 60 in response to the L-level load signal LOAD. In response to the L-level output signal, the inverter 60 supplies an H level second output signal SB to the NAND gate 61. The NAND gate 61 supplies the H-level third output signal SC to the D flip-flop 62 in response to the L-level load signal LOAD and the H-level second output signal SB.
When all of the set value data A1-A7 are "0, " the first to seventh FFs 51-57 sequentially perform the "preset operation" in response to the L-level load signal LOAD, and output the H-level output signals from their complementary output terminals. The NAND gate section 58 supplies an L-level first output signal SA to the RS flip-flop 59 in response to each H-level output signal. Next, the RS flip-flop 59 supplies the H-level output signal to the inverter 60 in response to the L-level first output signal SA. In response to the H-level output signal, the inverter 60 supplies an L level second output signal SB to the NAND gate 61. The second output signal SB falls to the L level from the H level in this manner. The NAND gate 61 continuously outputs the H-level third output signal SC in response to the L-level load signal LOAD and the L-level second output signal SB.
The up-counter section 50 starts counting the complementary frequency-divided signals CK and XCK after the "presetting", and the NAND gate section 58 outputs the H-level first output signal SA again in response to the up-count action.
When the load signal LOAD rises to the H level from the L level after the second output signal SB has fallen to the L level, the NAND gate 61 continuously outputs the H-level third output signal SC. As a result, the D flip-flop 62 always supplies the H-level modulus signal MDC to the prescaler, such that the frequency-dividing ratio of the prescaler is fixed.
FIG. 3 presents a time-line chart illustrating the operation of the swallow counter, as depicted in FIG. 1, when all of the set value data A1-A7 are "0" and the complementary frequency-divided signals CK and XCK have relatively high frequencies. The period in which the load signal LOAD maintains an L level in accordance with the high-frequency complementary frequency-divided signals CK and XCK becomes shorter than that in the case where the complementary frequency-divided signals CK and XCK have low frequencies (e.g., see discussion regarding FIG. 2). Therefore, the load signal LOAD rises to the H level from the L level while the second output signal SB is at the H level. Consequently, the NAND gate 61 outputs the L-level third output signal SC until the second output signal SB falls to the L level. As the D flip-flop 62 responds to the L-level third output signal SC and the inverter 63 responds to the H-level output signal, the L-level modulus signal MDC is supplied to the prescaler. As a result, the prescaler operates to change the frequency-dividing ratio. In other words, the frequency-dividing ratio is altered even though the prescaler is under the modulus control in which the frequency-dividing ratio should be fixed.
As such, malfunction of the circuit or device may result from the operational delays of the up-counter section 50 and the NAND gate section 58. When the frequencies of the complementary frequency-divided signals CK and XCK become high, the L-level duration of the load signal LOAD becomes shorter than the time from the point when all of the first to seventh FFs 51-57 perform the preset operation in response to the L-level load signal LOAD to the point when the NAND gate section 58 outputs the L-level first output signal SA. In other words, after the L-level duration of the load signal LOAD passes, the NAND gate section 58 outputs the L-level first output signal SA. Particularly, the preset operation of the first to seventh FFs 51-57 takes time, thus delaying the output of the L-level first output signal SA from the NAND gate section 58. As a result, the load signal LOAD rises to the H level from the L level before the second output signal SB falls to the L level from the H level. When the set value data A1-A7 are all set to "0", it takes time for the preset operation in which the first to seventh FFs 51-57 all respond to the L-level load signal LOAD to invert the output levels of the complementary output terminals to H from L. That is, the outputting of the H-level output signals from all the complementary output terminals is delayed.